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1 www.semtech.com sc1404 mobile multi-output pwm controller with virtual current sense tm power management description features applications typical application circuit the sc1404 is a multiple-output power supply controller designed to power battery operated systems. the sc1404 provides syn- chronous rectified buck converter control for two power supplies. an efficiency of 95% can be achieved. the sc1404 uses semtech?s proprietary virtual current sense tm technology along with external error amplifier compensation to achieve enhanced stability and dc accuracy over a wide range of output filter compo- nents while maintaining fixed frequency operation. the sc1404 also provides two linear regulators for system housekeeping. the 5v linear regulator takes its input from the battery; for efficiency, the output is switched to the 5v output when available. the 12v linear regulator output is generated from a coupled inductor off the 5v switching regulator. control functions include: power up sequencing, soft start, power- good signaling, and frequency synchronization. line and load regulation is to +/-1% of the output voltage. the internal oscilla- tor can be adjusted to 200 khz or 300 khz or synchronized to an external clock. the mosfet drivers provide >1a peak drive cur- rent for fast mosfet switching. the sc1404 includes a psave# input to select pulse skipping mode for high efficiency at light load, or fixed frequency mode for low noise operation. 6 to 30v input range (operation possible below 6v) 3.3v and 5v dual synchronous outputs fixed-frequency or psave for maximum efficiency over wide load current range 5v/50ma linear regulator 12v/200ma linear regulator virtual current sense tm for enhanced stability accurate low-loss current limiting out-of-phase switching reduces input capacitance external compensation supports wide range of output filter components for reduced cost programmable power-up sequence power good output output overvoltage & overcurrent protection with output undervoltage shutdown 4a typical shutdown current 6mw typical quiescent power notebook and subnotebook computers automotive electronics desktop dc-dc converters revision 4, july 2003 u4 sc1404 csh3 1 csl3 2 comp3 3 12out 4 vdd 5 sync 6 on5 7 gnd 8 ref 9 psave 10 reset 11 comp5 12 csl5 13 csh5 14 seq 15 dh5 16 phase5 17 bst5 18 dl5 19 pgnd 20 vl 21 v+ 22 shdn 23 dl3 24 bst3 25 phase3 26 dh3 27 run/on3 28 l1 + 4.7uf 10 + + t1 0.1uf c7 0.1uf 0.1uf 0.1uf 3 v o n /o f f s c 1404 o n /o f f i nput +6v to +30v + 0.1uf 5 v o n /o f f +2.5v ref pow er good +3v o u tp u t +5v alw ays o n + 4.7uf + 2.2uf + 12v o u tp u t +5v o u tp u t s c 1404 o n /o f f c11 0.22uf 0.1uf
2 ? 2003 semtech corp. www.semtech.com sc1404 preliminary power management electrical characteristics absolute maximum ratings r e t e m a r a pe d o cs n o i t i d n o cn i mp y tx a ms t i n u s r e l l o r t n o c s p m s n i a m e g n a r e g a t l o v t u p n in i v60 . 0 3v e g a t l o v t u p t u o v 3t u o 3 vt i m i l t n e r r u c o t a 0 = d a o l v 3 , v 0 3 o t 0 . 6 = + v3 2 . 33 . 37 3 . 3v e g a t l o v t u p t u o v 5t u o 5 vt i m i l t n e r r u c o t a 0 = d a o l v 5 , v 0 3 o t 0 . 6 = + v9 . 40 . 51 . 5v n o i t a l u g e r d a o lg r d l 3 v g r d l 5 v l v = # e v a s p , t i m i l t n e r r u c o t a 0 , s p m s r e h t i e4 . 0 -% n o i t a l u g e r e n i lg r i l 3 v g r i l 5 v l v = # e v a s p , v 0 3 < + v < 0 . 6 , s p m s r e h t i e5 0 . 0v / % unless otherwise noted: v+ = 15v, both pwms on, sync = 0v, vl load = 0ma, ref load = 0ma, psave# = 0v, t a =-40 to 85c. typical values are at t a = +25c. circuit = typical application circuit r e t e m a r a pn o i t p i r c s e dm u m i x a ms t i n u d n g o t 5 e s a h p , 3 e s a h p , + v , d d v s e g a t l o v e s a h p d n a y l p p u s0 3 + o t 3 . 0 -v d n g o t 5 e s a h p , 3 e s a h ps e g a t l o v e s a h p) c e s n 0 0 1 - t n e i s n a r t ( 0 . 2 -v d n g o t 5 h d , 3 h d , 5 t s b , 3 t s bs e g a t l o v t s o o b6 3 + o t 3 . 0 -v d n g o t d n g p d n u o r g l a n g i s o t d n u o r g r e w o p3 . 0 v d n g o t l vy l p p u s c i g o l6 + o t 3 . 0 -v ; 5 e s a h p o t 5 t s b ; 3 e s a h p o t 3 t s b y l p p u s e v i r d e t a g e d i s - h g i h6 + o t 3 . 0 -v 5 e s a h p o t 5 h d ; 3 e s a h p o t 3 h d s t u p t u o e v i r d e t a g e d i s - h g i h) 3 . 0 + x t s b + ( o t 3 . 0 -v d n g o t 5 l d , 3 l d d n g o t 3 h s c , 3 l s c , 5 h s c , 5 l s c s t u p t u o e v i r d e t a g e d i s - w o l s t u p n i e s n e s t n e r r u c d n a ) 3 . 0 + l v ( + o t 3 . 0 -v , # t e s e r , 5 n o , # e v a s p , q e s , c n y s , f e r d n g o t 5 p m o c , 3 p m o c , 5 b f , 3 b f , l v s t u p t u o / s t u p n i c i g o l) 3 . 0 + l v ( + o t 3 . 0 -v d n g o t # n d h s , 3 n o ) v 3 . 0 + + v ( + o t 3 . 0 -v d n g o t t r o h s f e r , l v s u o u n i t n o c t n e r r u c f e r 5 +a m t n e r r u c l v 0 5 +a m d n g o t t u o 2 1 ) 3 . 0 + d d v + ( o t 3 . 0 -v d n g o t t r o h s t u o 2 1 s u o u n i t n o c t n e r r u c t u o 2 1t n e r r u c t u p t u o v 2 10 0 2 +a m t j e g n a r e r u t a r e p m e t n o i t c n u j0 5 1 +c e c n a t s i s e r l a m r e h t e g a k c a pt n e i b m a o t n o i t c n u j6 7t t a w / c t s e g n a r e r u t a r e p m e t e g a r o t s0 0 2 + o t 5 6 -c t l e r u t a r e p m e t d a e l. x a m d n o c e s 0 1 , c 0 0 3 +c exceeding the specifications below may result in permanent damage to the device, or device malfunction. operation outside of th e parameters specified in the electrical characteristics section is not implied.
3 ? 2003 semtech corp. www.semtech.com sc1404 power management electrical characteristics cont. r e t e m a r a pe d o cs n o i t i d n o cn i mp y tx a ms t i n u s d l o h s e r h t t i m i l - t n e r r u c ) 2 e t o n ( p m i l 3 i p m i l 5 i n m i l 3 i n m i l 5 i h s c x l s c - x ) t n e r r u c e v i t i s o p ( h s c x l s c - x ) t n e r r u c e v i t a g e n ( 0 45 5 0 5 - 0 7v m d l o h s e r h t g n i s s o r c o r e z3 c z 5 c z h s c x l s c - x d e t s e t t o n , v 0 = # e v a s p5v m e m i t p m a r t r a t s - t f o s , t i m i l t n e r r u c l l u f % 5 9 o t e l b a n e m o r f f o t t c e p s e r h t i w c s o 2 1 5s k l c y c n e u q e r f r o t a l l i c s oi h c s o f o l c s o f l v = c n y s v 0 = c n y s 0 2 2 0 7 1 0 0 3 0 0 2 0 8 3 0 3 2 z h k r o t c a f y t u d m u m i x a mx a m 3 f d x a m 5 f d l v = c n y s v 0 = c n y s 2 9 4 9 4 9 6 9 % e s l u p h g i h t u p n i c n y sd e t s e t t o n0 0 3s n e s l u p w o l t u p n i c n y s h t d i w d e t s e t t o n0 0 3 e m i t l l a f / e s i r c n y sd e t s e t t o n0 0 2 y c n e u q e r f t u p n i c n y s e g n a r g r c n y s - 0 4 2 0 5 3 z h k t u p n i e s n e s - t n e r r u c t n e r r u c e g a k a e l 3 h s c i 5 h s c i v 0 . 5 = 5 h s c , v 3 . 3 = 3 h s c30 1a p m a r o r r e n i a g p o o l c d5 g c d , 3 g c d5 p m o c / 3 p m o c o t e d o n k c a b d e e f l a n r e t n i m o r f8 1v / v t c u d o r p h t d i w d n a b n i a g 8z h m e c n a t s i s e r t u p t u o5 c r , 3 c r5 p m o c , 3 p m o c5 2s m h o k e c n e r e f e r d n a r o t a l u g e r l a n r e t n i e g a t l o v t u p t u o l vt u o l v, v 0 3 < + v < v 6 ; + v = # n d h s i < a m 0 d a o l v 0 = 5 n o = 3 n o , a m 0 3 < 6 . 45 2 . 5v t u o k c o l e g a t l o v r e d n u l v d l o h s e r h t t l u a f v u l vv 7 . 0 = s i s e r e t s y h , e g d e g n i l l a f5 . 37 . 31 . 4 t u o k c o l r e v o h c t i w s l vw s l ve g d e g n i s i r - p u t r a t s t a r e v o h c t i w s5 . 4 e g a t l o v t u p t u o f e rt u o f e rd a o l l a n r e t x e o n5 4 . 25 . 25 5 . 2 n o i t a l u g e r d a o l f e r1 d l f e r 2 d l f e r i < a 0 d a o l a 0 5 <5 . 2 1v m i < a m 0 d a o l a m 5 <0 5 unless otherwise noted: v+ = 15v, both pwms on, sync = 0v, vl load = 0ma, ref load = 0ma, psave# = 0v, t a =-40 to 85c. typical values are at t a = +25c. circuit = typical application circuit
4 ? 2003 semtech corp. www.semtech.com sc1404 preliminary power management r e t e m a r a pe d o cs n o i t i d n o cn i mp y tx a ms t i n u t n e r r u c k n i s f e rk s f e r ie g a t l o v f e r n i e s i r v m 0 10 1a t u o k c o l t l u a f f e r e g a t l o v v u f e re g d e g n i l l a f8 . 12 . 2v g n i t a r e p o + v t n e r r u c y l p p u s p o p v i, n o s p m s v 5 , 5 t u o v o t r e v o d e h c t i w s l v i 5 d a o l i = 3 d a o l v 0 = # e v a s p , a 0 = 0 10 5a y b d n a t s + v t n e r r u c y l p p u s b s p v i; v 0 = # e v a s p , f f o s p m s h t o b , v 0 3 o t v 6 = + v # n d h s o t n i t n e r r u c s e d u l c n i 0 0 3 n w o d t u h s + v t n e r r u c y l p p u s d s p v iv 0 = # n d h s , v 0 3 o t v 6 = + v1 -35 1 r e w o p t n e c s e i u q n o i t p m u s n o c q ps p m s n o d a o l o n , d e l b a n e s p m s6w m n o i t c e t e d t l u a f p i r t e g a t l o v r e v o d l o h s e r h t v o 5 v , v o 3 ve g a t l o v t u p t u o d e d a o l n u o t t c e p s e r h t i w70 15 1% t l u a f - e g a t l o v r e v o y a l e d n o i t a g a p o r p v p i r t e g a t l o v r e v o e v o b a % 2 n e v i r d t u p t u o h t 5 . 1s t u p t u o e g a t l o v r e d n u d l o h s e r h t v u 5 v , v u 3 ve g a t l o v t u p t u o d e d a o l n u o t t c e p s e r h t i w5 65 75 8% t u p t u o e g a t l o v r e d n u e m i t t u o k c o l o t v u 3 v o t v u 5 v f o t t c e p s e r h t i w , d e l b a n e s p m s h c a e m o r f c s o 0 0 0 54 4 1 60 0 0 7s k l c l a m r e h t n w o d t u h s d l o h s e r h t c 0 1 = s i s e r e t s y h l a c i p y t0 5 1 +c # t e s e r p i r t # t e s e r d l o h s e r h t t s r 3 v t s r 5 v g n i l l a f , e g a t l o v t u p t u o d e d a o l n u o t t c e p s e r h t i w % 1 = s i s e r e t s y h l a c i p y t ; e g d e 2 1 -9 -5 -% # t e s e r y a l e d n o i t a g a p o r p p i r t # t e s e r w o l e b % 2 n e v i r d t u p t u o , e g d e g n i l l a f d l o h s e r h t 5 . 1s y a l e d # t e s e r e m i t l d s r 3 t l d s r 5 t f o t t c e p s e r h t i w c s o 0 0 0 , 7 20 0 0 , 2 30 0 0 , 7 3 s k l c s t u p t u o d n a s t u p n i w o l t u p n i c i g o l e g a t l o v , p o i v , 3 o i v , d s o i v , 5 o i v n s o i v c n y s , # n d h s , 5 n o , # e v a s p , 3 n o ) f e r = q e s ( 6 . 0v h g i h t u p n i c i g o l e g a t l o v , p h i v , 3 h i v , d s h i v , 5 h i v n s h i v c n y s , # n d h s , 5 n o , # e v a s p , 3 n o ) f e r = q e s ( 4 . 2v electrical characteristics cont. unless otherwise noted: v+ = 15v, both pwms on, sync = 0v, vl load = 0ma, ref load = 0ma, psave# = 0v, t a =-40 to 85c. typical values are at t a = +25c. circuit = typical application circuit
5 ? 2003 semtech corp. www.semtech.com sc1404 power management electrical characteristics cont. r e t e m a r a pe d o cs n o i t i d n o cn i mp y tx a ms t i n u t n e r r u c e g a k a e l t u p n i c n y s , 5 n o , # e v a s pn s l i , 5 l i , p l i f e r = q e s 1 -1 +a 3 n o - t n e r r u c e g a k a e l t u p n i3 l iv 5 1 = 3 n o2 -2 +a t n e r r u c e g a k a e l t u p n i # n d h s d s l iv 5 1 = # n d h s1 -3 0 1 +a e g a t l o v w o l t u p t u o c i g o ll t s r o va m 4 = k n i s i , # t e s e r4 . 0v t n e r r u c h g i h t u p t u o c i g o lh t s r o iv 5 . 3 = # t e s e r1a m e c n a t s i s e r n w o d - l l u p 5 n o5 n o r) f e r = q e s ( , v 0 = 3 n o , 5 n o0 0 1 ? e c r u o s / k n i s r e v i r d e t a g t n e r r u c , 3 h d i , 3 l d i 5 h d i , 5 l d i v 5 . 2 o t d e c r o f , 5 h d , 5 l d , 3 h d , 3 l d1a e c n a t s i s e r - n o r e v i r d e t a g, 3 p h g r , 3 h b g r , 5 p h g r , 5 h b g r 3 g l g r , 3 l v g r 5 g l g r , 5 l v g r , 3 e s a h p o t 3 h d , 3 h d o t 3 t s b , 5 e s a h p o t 5 h d , 5 h d o t 5 t s b , d n g p o t 3 l d , 3 l d o t l v d n g p o t 5 l d , 5 l d o t l v 5 . 17 ? d l o h s e r h t p a l r e v o - n o nt v o n zd n g o t 5 e s a h p , 3 e s a h p0 . 1v ) p a l r e v o - n o n ( h g u o r h t - t o o h s y a l e d e g d e g n i s i r x l d o t e g d e g n i l l a f x h d e g d e g n i s i r x h d o t e g d e g n i l l a f x l d o n , x l d d n a x h d n o d l o h s e r h t v 1 ( ) h d r o l d n o e c n a t i c a p a c l a n r e t x e 0 1 5 3 7 1 5 7 5 2 5 1 1 c e s n c e s n r o t a l u g e r r a e n i l v 2 1 d l o h s e r h t t n u h s d d vn h s d d v% 5 = s i s e r e t s y h , e g d e g n i s i r7 11 2v t n e r r u c t n u h s d d vt s d d v iv 0 2 = d d v50 10 3a m t n e r r u c e g a k a e l d d vk l d d v ie d o m y b d n a t s , v 5 = d d v0 3a e g a t l o v t u p t u o t u o 2 12 1 t u o va m 0 0 2 < d a o l < a m 05 5 . 1 11 . 2 15 7 . 2 1v t i m i l t n e r r u c t u o 2 12 1 m i l iv 3 1 = d d v , v 1 1 o t d e c r o f t u o 2 10 0 2a m d l o h s e r h t n o i t a l u g e r t u o 2 1r h t 2 1 ve g d e g n i l l a f9 . 1 1v t n e r r u c d d v t n e c s e i u qq 2 1 id a o l t u o 2 1 o n , e d o m n u r , v 8 1 = d d v0 80 0 1a notes: (1) this device is esd sensitive. use of standard esd handling procedures required. (2) applicable from 0 to +85c. unless otherwise noted: v+ = 15v, both pwms on, sync = 0v, vl load = 0ma, ref load = 0ma, psave# = 0v, t a =-40 to 85c. typical values are at t a = +25c. circuit = typical application circuit
6 ? 2003 semtech corp. www.semtech.com sc1404 preliminary power management pin descriptions note: all logic level inputs and outputs are open collector ttl compatible. # n i pe m a n n i pn o i t c n u f n i p 13 h s c. s p m s v 3 r o f t u p n i e s n e s t i m i l t n e r r u c . r o t s i s e r e s n e s t n e r r u c a f o e d i s r o t c u d n i e h t o t t c e n n o c 23 l s c. s p m s v 3 r o f t u p n i e s n e s e g a t l o v t u p t u o . r o t s i s e r e s n e s t n e r r u c a f o e d i s t u p t u o e h t o t t c e n n o c 33 p m o c. r e i f i l p m a r o r r e s p m s v 3 . 3 e h t f o t u p t u o e h t 4t u o 2 1. t u p t u o r o t a l u g e r r a e n i l l a n r e t n i v 2 1 5d d v e g a t l o v r e v o v 8 1 a o t y l l a n r e t n i s t c e n n o c o s l a . r o t a l u g e r r a e n i l t u o 2 1 e h t r o f t u p n i e g a t l o v y l p p u s . p m a l c r o t a l u g e r t n u h s 6c n y s 0 0 2 r o f d n g o t e i t ; n o i t a r e p o z h k 0 0 3 r o f l v o t e i t . t c e l e s y c n e u q e r f d n a n o i t a z i n o r h c n y s r o t a l l i c s o . z h k 0 5 3 d n a z h k 0 4 2 n e e w t e b r o t a l l i c s o l a n r e t x e n a o t e z i n o r h c n y s o t y l l a n r e t x e e v i r d . z h k 75 n o. t u p n i l o r t n o c f f o / n o v 5 8d n g. t n i o p e c n e r e f e r k c a b d e e f d n a d n u o r g g o l a n a e s i o n w o l 9f e r . m u m i n i m f 1 h t i w d n g o t s s a p y b . t u p t u o e g a t l o v e c n e r e f e r v 5 . 2 0 1# e v a s p . e s u l a m r o n r o f d n g o t t c e n n o c . h g i h n e h w e d o m e v a s p s e l b a s i d t a h t t u p n i c i g o l 1 1# t e s e r d e x i f a r e t f a h g i h s e o g # t e s e r . l v o t d n g m o r f s g n i w s # t e s e r . t u p t u o t e s e r d e m i t w o l - e v i t c a . p u r e w o p g n i w o l l o f y a l e d e l c y c k c o l c 0 0 0 , 2 3 2 15 p m o c. r e i f i l p m a r o r r e s p m s v 5 e h t f o t u p t u o e h t 3 15 l s c. s p m s v 5 r o f t u p n i e s n e s e g a t l o v t u p t u o . r o t s i s e r e s n e s t n e r r u c a f o e d i s t u p t u o e h t o t t c e n n o c 4 15 h s c. s p m s v 5 r o f t u p n i e s n e s t i m i l t n e r r u c . r o t s i s e r e s n e s t n e r r u c a f o e d i s r o t c u d n i e h t o t t c e n n o c 5 1q e s . # t e s e r y b d e s u ) s ( e g a t l o v r o t i n o m s t c e l e s d n a e c n e u q e s p u - r e w o p s p m s s t c e l e s t a h t t u p n i 6 15 h d. h c t i w s l e n n a h c - n e d i s - h g i h , v 5 e h t r o f t u p t u o e v i r d e t a g 7 15 e s a h p. n o i t c e n n o c ) r o t c u d n i ( e d o n g n i h c t i w s v 5 8 15 t s b. e v i r d e t a g e d i s - h g i h v 5 r o f n o i t c e n n o c r o t i c a p a c t s o o b 9 15 l dt e f s o m r e i f i t c e r s u o n o r h c n y s e d i s - w o l v 5 e h t r o f t u p t u o e v i r d e t a g 0 2d n g p. d n u o r g r e w o p 1 2l v. t u p t u o r o t a l u g e r r a e n i l l a n r e t n i v 5 2 2+ v. t u p n i e g a t l o v y r e t t a b 3 2# n d h s. w o l e v i t c a - t u p n i l o r t n o c n w o d t u h s 4 23 l d . t e f s o m r e i f i t c e r s u o n o r h c n y s e d i s - w o l v 3 e h t r o f t u p t u o e v i r d e t a g 5 23 t s b. e v i r d e t a g e d i s - h g i h v 3 r o f n o i t c e n n o c r o t i c a p a c t s o o b 6 23 e s a h p. n o i t c e n n o c ) r o t c u d n i ( e d o n g n i h c t i w s v 3 7 23 h d. h c t i w s l e n n a h c - n e d i s - h g i h v 3 e h t r o f t u p t u o e v i r d e t a g 8 23 n o. t u p n i l o r t n o c f f o / n o v 3
7 ? 2003 semtech corp. www.semtech.com sc1404 power management block diagram 2.5v ref v+ +3.3v vl vin vl bst3 dh3 lx3 dl3 csh3 csl3 comp3 ref time/on5 run/on3 seq reset comp5 csl5 csh5 pgnd dl5 lx5 dh5 bst5 vl sync v+ psav e 5v reg en delay csl5 vl ls osc ls hs vl 50mv 7.5m v 2.5m v 3v ctl logic oc ps pol 50mv 7.5m v 2.5m v oc ps pol 5v ctl logic pw m modulator pw m modulator ov fault +10% - 25% uv fault 3 vl 2 pow er-on sequence logic 0.5 2.0 ss timer bv delay +5v vin current ramp v+ csl3 csl5 12out vdd + 4.7 f 200m a 2.2 f + t1 1:3 12 v reg ps ps
8 ? 2003 semtech corp. www.semtech.com sc1404 preliminary power management pin configuration ordering information e c i v e de g a k c a pt ( . p m e t b m a ) r t s t i 4 0 4 1 c s8 2 - p o s s tc 5 8 + - 0 4 - r t s s i 4 0 4 1 c s8 2 - p o s s block diagram tssop-28/ssop-28 top view 3 h s c3 n o 3 l s c3 h d 3 p m o c3 e s a h p t u o 2 13 t s b d d v3 l d c n y s# n d h s 5 n o+ v d n gl v f e rd n g p # e v a s p5 l d # t e s e r5 t s b 5 p m o c5 e s a h p 5 l s c5 h d 5 h s cq e s sc1404 1 2 3 4 5 6 7 8 9 11 12 13 14 10 15 16 17 18 19 20 21 22 23 24 25 26 27 28 note: (1) only available in tape and reel packaging. a reel contains 2500 devices.
9 ? 2003 semtech corp. www.semtech.com sc1404 power management functional information detailed description the sc1404 is a versatile multiple-output power supply controller designed to power battery operated systems. out-of-phase switching improves signal quality and reduces input rms current, thereby reducing the size of input filter capacitors (see out-of- phase switching). the sc1404 provides synchronous rectified buck control in fixed-frequency forced-continuous mode and in hysteretic psave mode, for two switching converters over a wide load range. the two switchers have on-chip preset output voltages of 5.0v and 3.3v. the control and fault monitoring circuitry for each pwm controller includes digital softstart, turn-on sequencing, voltage error amplifier with built-in slope compensation, pulse width modulator, power save, over-current, over-voltage and under- voltage fault protection. two linear regulators and a precision reference voltage are also provided. the 5v/50ma linear regulator (vl supply) which powers the sc1404 and gate drivers operates from the battery (v+ supply). if the 5v converter is running, the sc1404 disables the linear regulator and connects the vl supply to the 5v output through an internal switch. the operating current for the sc1404 and gate drivers then comes from the more efficient 5v converter. the 12v/200ma linear regulator can supply 200ma. semtech?s proprietary virtual current sense tm provides advantages in stability and signal to noise ratio compared to conventional current sensing. pwm control there are two separate pwm control blocks for the 3v and 5v switchers. they are switched out-of-phase with each other. the interleaved topology offers advantages over in-phase solutions. it reduces steady state input filter requirements by reducing current drawn from the filter capacitors. to avoid both switchers switching simultaneously, there is a built-in time delay between the two switchers, the amount of which depends on the input voltage (see out-of-phase switching). the pwm provides two modes of control over the entire load range: 1 - forced continuous conduction mode as a fixed-frequency peak current mode controller with falling edge modulation, and 2 - hysteretic power-save mode. current sense is done differently than that in the conventional peak current mode control. semtech?s proprietary virtual current sense tm emulates the necessary inductor current information for proper functioning of the ic. when the switcher operates in continuous conduction mode, the high-side mosfet turns on the beginning of each switching cycle. it is turned off when the desired duty cycle is reached. active shoot- through protection will delay the low-side mosfet turn-on until the phase node drops below 1.0 v. the low-side mosfet then remains on until the beginning of the next switching cycle. again, active shoot-through protection ensures that the gate to the low- side mosfet has dropped low before the high-side mosfet is turned on. under light load conditions when the psave pin is low, the sc1404 operates as a hysteretic controller in discontinuous conduction mode to reduce switching frequency and switching bias current. the switching frequency then is determined by the hysteretic trip voltage set around the reference. when entering psave# mode, if the minimum (valley) inductor current as measured across the csh and csl pins is below the psave# threshold for four switching cycles, the virtual current sense circuitry is shutdown and pwm control switches from forced continuous to hysteretic mode. if the minimum (valley) inductor current is above the threshold for four switching cycles, pwm control changes from hysteretic to forced continuous mode. the sc1404 provides built-in hysteresis to prevent chattering between the two modes of operation. gate drive / control the sc1404 gate drivers are designed to switch large mosfets up to 350khz. the high-side gate driver is required to drive the gate of high-side mosfets above the v+ input. the supply for the gate drivers is generated by charging a boostrap capacitor from the vl supply while the low-side driver is on. monitoring circuitry ensures that the bootstrap capacitor is charged when coming out of shutdown or fault conditions where the bootstrap capacitor may be depleted. in continuous conduction mode, the low-side driver output that controls the low-side mosfet is on when the high-side driver is off. under light load conditions when the psave# input is low, the inductor ripple current will approach the point where it reverses polarity. this is detected by the low-side driver control and the low-side mosfet is turned off before the current goes significantly negative and causes energy drain from the output. the low-side driver operation is also affected by various fault conditions as described in the fault protection section. external compensation the comp pin allows external compensation of the feedback loop. this allows greater flexibility when choosing output filters, resulting in reduced cost and smaller size compared to a fixed compensation approach. a nominal gain of 18 for the error amplifier improves the system loop gain and output transient response. internal bias supply the vl linear regulator provides a 5v output that powers the gate drivers, 2.5v reference, and internal controls of the sc1404. the vl supply can provide up to 50ma, but this must include mosfet gate drive current. the vl pin should be bypassed to gnd with 4.7uf to supply the peak gate drive curents. the vl regulator receives input power from the v+ battery input. efficiency is im- proved by providing a boot-strap for the vl bias. when the 5v smps output voltage reaches 5v, internal circuitry detects this condition and turns on a pmos pass device between csl5 and vl. the internal vl regulator is then disabled and the vl bias is pro- vided by the high efficiency 5v switcher.
10 ? 2003 semtech corp. www.semtech.com sc1404 preliminary power management functional information current sense (csh, csl) the output current of the power supply is sensed as the voltage drop across an external resistor between the csh and csl pins. overcurrent is detected when the current sense voltage exceeds +/- 50mv. a positive overcurrent will turn off the high-side driver, a negative overcurrent will turn off the low-side driver; each on a cycle-by-cycle basis. oscillator when the sync pin is set high the oscillator runs at 300khz; when sync is set low the frequency is 200khz. the oscillator can also be synchronized to the falling edge of a clock on the sync pin with a frequency between 240khz and 350khz. in general, 200khz operation is used for highest efficiency while 300khz leads to less output ripple and/or smaller filter components. fault protection in addition to cycle-by-cycle current limit, the sc1404 monitors over-temperature, and output overvoltage and undervoltage conditions. the overtemperature detection will shut the part down if the die temperature exceeds 150 c with 10 c of hysteresis. if either smps output is more than 10% above its nominal value, both smps are latched off and the low-side mosfets are latched on. to prevent the output from ringing too far below ground in a fault condition, a 1a schottky diode should be placed across each output. two different levels of undervoltage are detected. if the output falls 10% below its nominal output, the reset# output is pulled low.if the output falls 25% below its nominal output following a start-up delay, both smps are latched off. both of the latched fault modes persist until shdn# or on3 is toggled, or the v+ input is brought below 1v. power up controls and soft start the user has control of the sc1404 reset# by setting the seq, on3 and on5 pins as described in the following table. at startup, the reset# pin is held low for 32k switching cycles. another timer is used to enable the undervoltage protection. the undervoltage protection circuitry is enabled after 6144 switching cycles, at which time the smps should be in regulation. when seq is set to ref, the reset# only monitors the 3.3v smps and the 5v smps is ignored. each smps contains its own counter and dac to gradually increase the current limit at startup to prevent surge currents. the current limit is increased from 0, 20%, 40%, 60%, 80%, to 100% linearly over the course of 512 switching cycles. 12out supply the 12out linear regulator is capable of supplying 200ma. the input voltage to the 12out regulator is generated by a secondary winding on the 5v smps inductor. a heavy load on the 12out regulator when the 5v smps is in psave will cause the vdd input to drop, browning out the regulator. if the output drops 0.8% from its nominal value, the 5v smps is forced out of psave mode and into continuous conduction mode for several cycles. this recharges the bulk input capacitor on the vdd. the 12out linear regulator also has a current limit to prevent damage under short circuit conditions. over-voltage protection is provided on the vdd input. if the vdd input is above 19v, an over-voltage is detected and a 10ma current shunt load is applied to vdd. the over-voltage threshold has a 0.5v hysteresis. shutdown and operating modes holding the shdn# pin low disables the sc1404, reducing the v+ input current to less than 10ua. when shdn goes high, the part enters a standby mode where the vl regulator and vref are enabled. turning on either smps will put the sc1404 in run mode. # n d h s# n d h s # n d h s # n d h s# n d h s3 n o3 n o 3 n o 3 n o3 n o5 n o5 n o 5 n o 5 n o5 n oe d o me d o m e d o m e d o me d o mn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e d w o lxx n w o d - t u h ss a i b m u m i n i m t n e r r u c h g i hw o lw o ly b d n a t sl v d n a f e r v r o t a l u g e r e l b a n e h g i hh g i hh g i hn u r e d o m s p m s h t o b g n i n n u r g n i d a o l ( e c n a t s i s e r ? ) 1 1 5k 7 6 . 2k 9 . 9 4k 5 5 2g e m 1 m o r f n o i t a i v e d v 0 2 9 4 . 2 = f e r v v m 3 . 8v m 1 . 3v m 5 . 0v m 3 . 0v m 0 the ref output is accurate to +/- 2% over temperature. it is ca- pable of delivering 5ma max and should be bypassed with 1uf minimum. loading the ref pin will reduce the ref voltage slightly.
11 ? 2003 semtech corp. www.semtech.com sc1404 power management sc1404 startup sequence chart reference circuit design introduction the sc1404 is a versatile dual switching regulator with fixed 5v and 3.3v outputs . in addition, there is an on-chip 5v linear regulator capable of supplying 50ma output current and a 12v linear regulator able to provide 200ma. the sc1404 is designed for notebook applications but has is suited to applications where high efficiency, small package, and low cost are required. design guidelines the schematic for the reference circuit is shown on page 22. the reference circuit is configured as follows: switching regulator 1 vout1 = 3.3v @ 6a switching regulator 2 vout2 = 5.0v @ 6a linear regulator 1 vout3 = 12v, 200ma linear regulator 2 vout3 = 5.0v @ 50ma designing the output filter before calculating the output filter inductance and output capacitance, an acceptable amount of output ripple current must be determined. the maximum allowable ripple current depends on the transient requirement of the power supply. under normal situation, the ripple current is usually set around 10 to 20% of the functional information maximum load. however, in order to speed up the output transient response, ripple current can be much higher. in this design, we are going to set the ripple current to be 40% of maximum load. so once the ripple voltage specification is determined, the capacitor esr is chosen. the output ripple voltage is usually specified at +/ - 1% of the output voltage. for the reference circuit 3.3v switcher, we selected a maximum ripple voltage of 33mv. choosing one 180uf, 4v panasonic sp polymer aluminum electrolytic cap, of which esr is 15 ? m , sets the maximum ripple current as follows: checking to see if the maximum rms current can be met by the sp cap. irms=0.635 a << irms_rated=3.0a the output inductance can now be found by: q e s3 n o5 n o# t e s e rn o i t p i r c s e d f e rw o lw o l. s p m s v 3 . 3 s w o l l o f . f f o s s p m s h t o b . e d o m l o r t n o c t r a t s t n a d n e p e d n i f e rw o lh g i h. w o l. f f o s p m s v 3 . 3 , n o s p m s v 5 f e rh g i hw o l. s p m s v 3 . 3 s w o l l o f. f f o s p m s v 5 , n o s p m s v 3 . 3 f e rh g i hh g i h. s p m s v 3 . 3 s w o l l o f. n o s s p m s h t o b d n gw o lx . w o l. f f o s s p m s h t o b d n gh g i hw o l / h g i hn i e r a s t u p t u o h t o b r e t f a h g i h . n o i t a l u g e r s i v 3 , h g i h = 5 n o f i . h g i h s e o g 3 n o n e h w s t r a t s v 5 . f f o s i v 3 , w o l = 5 n o f i . n o l vw o lx . w o l. f f o s s p m s h t o b l vh g i hw o l / h g i hn i e r a s t u p t u o h t o b r e t f a h g i h . n o i t a l u g e r s i v 5 , h g i h = 5 n o f i . h g i h s e o g 3 n o n e h w s t r a t s v 3 . f f o s i v 5 , w o l = 5 n o f i . n o applications information 3 i i i i i 2 2 2 1 2 1 rms + ? + = o s nom o nom _ in o i t d ) v v ( l ? ? ? ? = esr v i max _ o o ? = ? a 2 . 2 015 . 0 v 033 . 0 i o = ? = ? 2 i i o 1 ? ? = 2 i i o 2 ? + =
12 ? 2003 semtech corp. www.semtech.com sc1404 preliminary power management applications information where vin_nom=15v, vo=3.3v, d=vo/vin_nom, fs=300khz, ts=3.33us and ? ? ? ? ? io=2.2 a. lo is then calculated to be 3.9uh. for the interest of this design, lo is chosen to be 4.7uh for the 3.3v output. for the 5v output, a coupled inductor with 6.4uh primary (5v winding) inductance is used. choosing current sense resistor since the sc1404 implements virtual current sense tm , an exter- nal current sense resistor is not needed by the control loop. but it is required for cycle-by-cycle current limit. cycle-by-cycle current limit is reached when the voltage across the current sense resis- tor exceeds 50mv nominal. depending on the system require- ment, this current limit can vary, it is usually 10 to 30% higher than the maximum load. taking into consideration lower limit of the 50mv, the value of the current sense resistor can be calculated using the following equation: for a dc oc trip point between 8 to 12a, rsense is chosen to be 5m ? . choosing the main switching mosfet before choosing the main switch mosfet, we need to know two critical parameters: voltage and current rating. in order to mini- mize the conduction loss, we recommend using the lowest rds(on) for the same voltage and current rating. the maximum drain to source voltage of the switch mosfet is mainly decided by the topology of the switcher. since this is a buck topology, applying a derating of 70%, a 30v mosfet is used in the design. the peak current of the mosfet is determined by the following calculations are done to verify that the power dissi- pation of the main switch mosfet is well within 1.86w, which is the maximum allowable power dissipation for the package. where rds(on) = 0.01 ? @tj=25 c and vgs = 4.5v. in order to find rds(on)@ tj=100 c , use 1.40*rds(on)@25 c . therefore, rds(on) @ tj = 100 c is equal to 0.014 ? . where = 7.1a, = 4.9a and the worst case conduction loss is calculated to be 25mw. and the switching loss of the mosfet is given by, where crss is the reverse transfer capacitance of the mosfet; it is equal to 200pf for sts12nf30l, ig is the gate driver current; it is equal to 1a for sc1404. and vin_nom = 15v, fs = 300khz. the switching loss is calculated to 81mw. and the gate loss is given by, where cg=11nf, v=5v and fs=300khz. the gate loss is calcu- lated to be 41mw. so the total power dissipation is calculated to be 147mw and is well within the maximum power dissipation allowance of the mosfet. no special heating sinking is required when laying out the mosfet. according to the calculated voltage and current rating, si4886dy, irf7413, fds9412 or sts12nf30l meets the requirement. the specs for these mosfets are listed in the table below. for the purpose of this exercise, sts12nf30l is chosen. next step is to determine its power handling capability. based on 85 c ambient temperature, 150 c junction temperature and 50 c /w ther- mal resistance, its power handling is calculated as follows: t j = 150c; t a = 85c; = 50c/w r o d n e v n / p ) v ( s d v) a ( d i @ ) n 0 ( s d r ) m h o ( v 5 . 4 e g a k c a p y d 6 8 8 4 i s0 33 15 3 1 0 . 08 - o s 3 1 4 7 f r i0 33 11 1 0 . 08 - o s 2 1 4 9 s d f0 39 . 76 3 0 . 08 - o s - 3 f n 2 1 s t s l 0 0 32 15 8 0 0 . 08 - o s ja s 2 g gate f v c 2 1 p ? ? ? = nom 2 2 2 1 2 1 rms d ) 3 i i i i ( i ? + ? + = gate switching conduction diss _ total p p p p + + = nom 2 rms ) on ( ds conduction d i r p ? ? = g out s 2 in rss switching i i f v c p ? ? ? = nom _ in out nom v v d = v 21 v v max _ in max _ ds = = 2 i i i max _ o max 2 ? ? = 1.30w 50 85 150 t t p ja a j t = ? = ? = a 11 m 5 . 5 mv 60 i peak = ? = oc _ pk (min) sense i mv 40 r = 2 i i i max _ o max 1 ? + =
13 ? 2003 semtech corp. www.semtech.com sc1404 power management applications information applications information designing the loop there are two aspects concerning the loop design. one is the power train design and the other is the external compensation design. a good loop design is a combination of the two. in the sc1404, the control-to-output/power train response is dominated by the load impedance, the effective current sense resistor, out- put capacitance, and the esr of the output caps. the low fre- quency gain is dominated by the output load impedance and the effective current sense resistor. inherent to virtual current sense tm , there is one additional low frequency pole sitting between 100hz and 1khz and a zero between 15khz and 25khz. to compensate for the sc1404 is easy since the output of error amplifier comp pin is available for external compensation. a traditional pole-zero- pole compensation is not necessary in the design using sc1404. to ensure high phase margin at crossover frequency while mini- mizing the component count, a simple high frequency pole is of- ten sufficient. in the reference design below, single-pole compen- sation method is demonstrated. and the loop measurement re- sults are compared to that obtained from the simulation model. transient response is also done to validate the model. also, to help speeding up the design process, a list of recommended out- put caps vs. compensation caps value is given in table i. single-pole compensation method given parameters: vin = 19v, vout = 3.3v @ 2.2a, output impedance, ro = 3.3v/2.2a = 1.5 ? , panasonic sp cap, co = 180uf, resr = 15 ? m , output inductor, lo = 4.7uh switching frequency, fs = 300khz simulated control-to-output gain & phase response (up to 100khz) is plotted below . . measured control-to-output gain & phase response (up to 100khz) is plotted below. -50 -40 -30 -20 -10 0 10 20 30 40 50 1.00e+02 1.00e+03 1.00e+04 1.00e+05 f (hz) gain (db) -200 -150 -100 -50 0 50 100 150 200 1.00e+02 1.00e+03 1.00e+04 1.00e+05 f (hz) phase (deg) -50 -40 -30 -20 -10 0 10 20 30 40 50 1.00e+02 1.00e+03 1.00e+04 1.00e+05 f (hz) gain (db) -200 -150 -100 -50 0 50 100 150 200 1.00e+02 1.00e+03 1.00e+04 1.00e+05 f (hz) phase (deg) single-pole compensation of the error amplifier is achieved by connecting a 100pf capacitor from the comp pin of the sc1404 to ground. the simulated feedback gain & phase response (up to 100khz) is plotted below.
14 ? 2003 semtech corp. www.semtech.com sc1404 preliminary power management applications information simulated overall gain & phase responses (up to 100khz) is plot- ted below. measured feedback gain & phase responses (up to 100khz) is plotted below. -15 -10 -5 0 5 10 15 20 25 1.00e+02 1.00e+03 1.00e+04 1.00e+05 f (hz) gain (db) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 1.00e+02 1.00e+03 1.00e+04 1.00e+05 f (hz) phase (deg) -80 -60 -40 -20 0 20 40 60 80 1.00e+02 1.00e+03 1.00e+04 1.00e+05 f (hz) gain (db) -20 0 20 40 60 80 100 120 140 160 180 1.00e+02 1.00e+03 1.00e+04 1.00e+05 f (hz) phase (deg) -15 -10 -5 0 5 10 15 20 25 1.00e+02 1.00e+03 1.00e+04 1.00e+05 f (hz) gain (db) -180 -160 -140 -120 -100 -80 -60 -40 -20 0 20 1.00e+02 1.00e+03 1.00e+04 1.00e+05 frequency (hz) phase (deg)
15 ? 2003 semtech corp. www.semtech.com sc1404 power management applications information measured overall gain & phase response of the single-pole com- pensation using sc1404 is plotted below. table i. recommended compensation cap for different output capacitance. table i. is useful only if the following esr condition is satisfied. fo > 50khz where resr is the equivalent esr of the total output caps. for instance, if two panasonic sp cap 180uf, 15 ? m are used. the equivalent resr = esr(single)/2 = 7.5 ? m . -20 0 20 40 60 80 100 120 140 160 180 1.00e+02 1.00e+03 1.00e+04 1.00e+05 f (hz) phase (deg) -80 -45 -10 25 60 1.00e+02 1.00e+03 1.00e+04 1.00e+05 f (hz) gain (db) the error amplifier compensation is set by the internal output resistance of the amplifier (25 kohms typical) and the external impedance attached to the comp pin. connecting a single ca- pacitor to the comp pin places a r-c pole into the error amplifier. o esr o c r 2 1 f ? ? ? = output cap recommended compensation cap value <= 180uf 100pf >1000uf 330pf >180uf & < 1000uf 200pf
16 ? 2003 semtech corp. www.semtech.com sc1404 preliminary power management applications information the sc1404 uses out-of-phase switching between the two converters to reduce input ripple current, enabling the use of smaller, cheaper input capacitors when compared to in-phase switching. the two approaches are shown in the following figures. the first figure shows in-phase switching: i3in is the input current drawn by the 3.3v converter, i5in is the input current drawn by the 5v converter. the two converters start each switching cycle simultaneously, resulting in a significant amount of overlap. this overlap increases the peak current. the total input current to the converter is the third trace iin, which shows how the two currents add together. the fourth trace shows the current flowing in and out of the input capacitors. in-phase switching the next figure shows out-of-phase switching. since the 3.3v and 5v converters are spaced apart, there is no resulting overlap. this results in a two benefits; the peak current is reduced and the frequency content is higher, both of which make filtering easier. the third trace shows the total input current, and the fourth trace shows the current in and out of the input capacitors. the rms value of this current is significantly lower than the in-phase case and allows for smaller capacitors due to reduced rms current ratings. out-of-phase switching as the input voltage is reduced, the duty cycle of both converters increases, as shown in the following figure. for inputs less than 8.3 volts it is impossible to prevent overlap when producing 3.3v and 5v outputs, regardless of the phase relationship between the converters. e g a t l o v t u p n ig n i s i r r e t r e v n o c v 3 m o r f d a e l e s a h p e g d e g n i s i r r e t r e v n o c v 5 o t e g d e v 6 . 9 > n i vd o i r e p g n i h c t i w s f o % 1 4 v 7 . 6 > n i v > v 6 . 9d o i r e p g n i h c t i w s f o % 9 5 n i v > 7 . 6d o i r e p g n i h c t i w s f o % 4 6 from an input filter standpoint it is desirable to minimize the overlap, but it is also desirable to keep the turn-on and turn-off transitions of the two converters separated in time, otherwise the two converters may affect each other due to switching noise. the sc1404 implements this by changing the phase relationship between the converter depending on the input voltage. vin > 9.6v: 3.3v turn-on leads 5v turn-on by 41% of the switching period. with vin > 9.6v it is always possible to achieve no overlap, which minimizes the input ripple current. at vin = 9.6v there is no overlap, but the 3.3v turn-on is nearing the 5v turn-off. 6.7 < vin < 9.6v: 3.3v turn-on leads 5v turn-on by 59% of the period. to prevent the 3v turn-on from coinciding with the 5v turn-off (which could adversely affect either output), the 5v pulse is delayed in time slightly such that the 3v turn-on occurs before the 5v turn-off. this creates a small overlap between the 3v turn-on and the 5v turn-off, with a resulting slight increase in rms input ripple, but this is preferred since it greatly reduces noise problems caused by simultaneous transitions. note that at vin = 6.7, the 3v turn-off is nearing the 5v turn-on. input capacitor selection/out-of-phase switching i3in i5in iin 0 average icap 0 period phase lead i3in i5in iin average ica p 0 0 icap iin average 0 0 i3in i5in
17 ? 2003 semtech corp. www.semtech.com sc1404 power management typical characteristics choosing synchronous mosfet and schottky diode since this is a buck topology, the voltage and current ratings of the synchronous mosfet are similar to the high-side mosfet. it makes sense cost-volume-wise to use the same mosfet for both the main switch and synchronous mosfet. therefore, sts12nf30l is used again in the design for synchronous mosfet. to improve overall efficiency, an external schottky diode is used in parallel to the synchronous mosfet. the freewheeling current goes into the schottky diode instead of the body diode of the synchronous mosfet, which usually has very high forward drop and slow tran- sient behavior. it is important when laying out the board to place both the synchronous mosfet and schottky diode close to each other to reduce the current ramp-up and ramp-down time due to parasitic inductance between the channel of the mosfet and the schottky diode. the current rating of the schottky diode can be determined by the following equation. the sc1404 will operate below 6v input voltage with careful design, but there are limitations. the first limitation is the maximum available duty cycle from the sc1404, which limits the obtainable output voltage. the design should minimize all circuit losses through the system in order to deliver maximum power to the output. a second limitation with operation below 6v is transient response. when load current increases rapidly, the output voltage drops slightly; the feedback loop normally increases duty cycle briefly to bring the output voltage back up. if duty cycle is already near the maximum limit, the duty cycle cannot increase enough to meet the demand, and the output voltage sags more than normal. this problem can not be solved by changing the feedback compensation, it is a function of the input voltage, duty cycle, and inductor and capacitor values. if an application requires 5v output from an input voltage below 6v, the following guidelines should be used: 1 - set the switching frequency to 200 khz (tie sync to gnd). this increases the maximum duty cycle compared to 300 khz operation. 2 - minimize the resistance in the power train. select mosfets, inductor, and current sense resistor to provide the lowest resistance as is practical. 3 - minimize the pcb resistance for all traces carrying high current. this includes traces to the input capacitors, mosfets and diodes, inductor, current sense resistor, and output capacitor. 4 - minimize the resistance between the sc1404 circuit and the power source (battery, battery charger, ac adaptor). 5 - use low esr capacitors on the input to prevent the input voltage dropping during on-time. 6 - if large load transients are expected, high capacitance and low esr capacitors should be used on both the input and output. a 2 . 0 t n 100 i i s load avg _ f = ? = vin < 6.7 volts: 3.3v turn-on leads 5v turn-on by 64% of the period. the 5v turn-on is delayed slightly more to add separation between the 3v turn-off and 5v turn-on. this leads to more overlap, but at this point overlap is unavoidable. input ripple current calculations: the following equations provide quick approximations for input ripple current: d3 = 3.3v duty cycle = 3.3/vin d5 = 5v duty cycle = 5/vin i3 = 3.3v load current i5 = 5v load current dovl = overlapping duty cycle of the 3v and 5v pulses, which varies according to input voltage: vin > 9.6v: dovl = 0 9.6v > vin > 6.7v: dovl = d5 - 0.41 6.7v > vin dovl = d5 - 0.36 iin = d3 . i3 + d5 . i5 (average current drawn from vin) (isw_rms) 2 = dovl . (i3 + i5) 2 + (d3 - dovl) . i3 2 + (d5 -dovl) . i5 2 isw_rms = rms current flowing into 3v and 5v smps irms_cap = isw_rms 2 iin 2 + the worst-case ripple current varies by application. for the case of i3 = i5 = 6a, the worst-case ripple occurs at vin = 7.5v, at which point the rms capacitor ripple current is 4.2 amps. to handle this the reference design uses 4 paralleled ceramic capacitors, (murata grm32nf51e106z, 10 uf 25v, size 1210). each capacitor is rated at 2.2 amps, allowing for derating at higher temperatures. where 100nsec is the estimated time between the mosfet turn- ing off and the schottky diode taking over and ts = 3.33us. there- fore a schottky diode with a forward current of 0.5a is sufficient for this design. operation below 6v input
18 ? 2003 semtech corp. www.semtech.com sc1404 preliminary power management 5v start-up with slow vin ramp. proper startup of the 5v output can be hampered by slow dv/dt on the input. the sc1404 will power up and attempt to generate an output when the input voltage exceeds 4.5 volts. if the input has a slow dv/dt, the input voltage will not rise significantly during the start-up sequence, leading to two conditions. first, the vl supply can be hundreds of mv below 5v, since the input may not yet be above 5v. second, the duty cycle will be at maximum, leading to very small off-times. these two conditions tend to reduce the boost voltage; if continued indefinitely, the boost capacitor may be unable to recharge fully, and eventually the high-side driver loses its boost bias. to avoid this the following steps should be taken: 1. if possible the dv/dt of the input supply should exceed .02v/ usec. this dv/dt condition only applies when the input passes between 4 and 6 volts, the point at which the sc1404 begins a startup sequence. an alternative is to make sure the input voltage reaches 6 volts within 100 usec of sc1404 startup at approximately 4.2 volts. this is sufficiently fast to allow vl and duty cycle to achieve normal levels and will prevents the boost voltage from falling. 2. if the dv/dt of the input cannot meet condition 1, the startup of the sc1404 should be delayed until the input voltage reaches 6v. this can be done using either the shdn# or on5 pin. if the dv/dt is moderate (slews from 4 to 6 volts in several msecs), an rc delay on either the shdn# or on5 pin should be enough to delay turn-on until the input reaches 6v. 3. for slow dv/dt on the input (10?s of msec), the sc1404 should be held off until the input reaches 6v. this can be done using a comparator or external logic to hold the shdn# or on5 pin low until the input reaches 6v. 12v load limitations the 12v regulator derives input power from a secondary winding on the 5v inductor. during the 5v off-time, the inductor transfers energy from the 5v winding to the secondary winding, thereby providing a crudely regulated 15v that feeds the 12v regulator. note that duty cycle increases at low input voltages, and therefore the on-time decreases. at low input voltages, the duty cycle increases to maintain the 5v output. the off-time consequently decreases, which has two detrimental effects. it allows less time to recharge the raw 15v capacitor, and it also raises the peak 15v current required to maintain the average 12v load. the 15v winding needs higher peak current, delivered in less time. but the stray (leakage) inductance of the inductor resists rapid changes in winding current, and ultimately limits how much current can be drawn from 15v before the voltage falls. e g n a r n i ve g n a r n i v e g n a r n i v e g n a r n i ve g n a r n i vs n o i t i d n o c d a o l v 2 1s n o i t i d n o c d a o l v 2 1 s n o i t i d n o c d a o l v 2 1 s n o i t i d n o c d a o l v 2 1s n o i t i d n o c d a o l v 2 1 >v 0 1d a o l v 2 1< d a o l v 5 * 2 / 1 x a m a m 0 0 2 = d a o l v 2 1 v 0 1 - v 7d a o l v 2 1< d a o l v 5 * 2 / 1 : d a o l v 2 1 e t a r e d y l r a e n i l v 0 1 t a a m 0 0 2 v 7 t a a m 0 0 1 v 7 - v 6d a o l v 2 1< d a o l v 5 * 2 / 1 : d a o l v 2 1 e t a r e d y l r a e n i l v 0 1 t a a m 0 0 1 v 7 t a a m 5 2 the following guidelines for 12v loading apply to the typical circuit, page 22. psave operation the sc1404 enters power-save operation if the load is sufficiently light, and if psave is tied low. in psave operation, the switching frequency is no longer fixed, and the converter operates as a hysteretic converter. this reduces gate drive losses and other switching losses to improve efficiency. each converter willl enter or exit psave operation independently, based on load current. the hysteresis (output ripple) on the 5v output is typically 70mv, and the 3v hysteresis is typically 35mv.
19 ? 2003 semtech corp. www.semtech.com sc1404 power management overvoltage test measuring the overvoltage trip point can be problematic. any buck converter with synchronous mosfets can act as a boost converter, sending energy from output to input. in some cases the energy sent to the input is enough to drive the input voltage be- yond normal levels, causing input overvoltage. to prevent this, enable the sc1404 psave# feature, which effectively disables the low side mosfet drive so that little energy, if any, is transferred back to the input. semtech recommends the following circuit for measuring the ov- ervoltage trip point. d1 prevents the output voltage from damag- ing lab supply 1. r1 limits the amount of energy that can be cycled from the output to the input. r2 absorbs the energy that might flow from output to input, and d2 protects lab supply from pos- sible damage. the on5 signal is monitored to indicate when overvoltage occurs. initial conditions: both lab supplies set to zero volts no load connected to 3v or 5v psave# enabled (psave# tied to gnd) on5 enabled on3 enabled dvms monitoring on5 and the output under test. oscilloscope probe connected to phase node of the output under test (not strictly required). set lab supply 2 to provide 10v at the sc1404 input. the phase node of the output being tested should show some switching ac- tivity. the on5 pin should be above 4v. slowly increase lab supply 1 until the output under test rises slightly above it?s normal dc level. as lab supply 1 increases, switching activity at the phase node will cease. the on5 pin should remain above 4v. increase lab supply 1 in very small increments, monitoring both on5 and the output under test. the overvoltage trip point is the highest voltage seen at the output before on5 pulls low (approxi- mately 0.3v). do not record the voltage seen at the output after on5 has pulled low; when on5 pulls low, the current flowing in d1 changes, corrupting the voltage seen at the output. 1k d1 e.g. 1n4004 r2 75 to dvm d1 e.g. 1n4004 vin supply r1 470 2 sc1404 evaluation board lab output test under 1 supply lab to dvm 1/2w on5 vl 1/2w
20 ? 2003 semtech corp. www.semtech.com sc1404 preliminary power management as with any high frequency switching regulator design, a good pcb layout is very essential in order to achieve optimum noise, effi- ciency, and stability performance of the converter. before starting to layout the pcb, a careful layout strategy is strongly recom- mended. see the pcb layout in the sc1404 evaluation kit manual for example. in most applications, we recommend to use fr4 with 4 or more layers and at least 2 oz copper (for output current up to 6a). use at least one inner layer for ground connection. and it is always a good practice to tie signal ground and power ground at one single point so that the signal ground is not easily contami- nated. also be sure that high current paths have low inductance and resistance by making trace widths as wide as possible and lengths as short as possible. properly decouple lines that pull large amounts of current in short periods of time. the following step by step layout strategy should be used in order to fully utilize the potential of sc1404. step #1. power train components placement. a. power train arrangement. place power train components first. the figure below shows the recommended power train arrangement. q1 is the main switching fet, q2 is the synchronous rectifier fet, d1 is the schottky diode and l1 is the output inductor. the phase node, where the source layout guidelines q2 d1 q1 l1 of the upper switching fet and the drain of the synchronous recti- fier meets, since it switches at very high rate of speed, is generally the largest source of common-mode noise in the converter circuit. it should be kept to a minimum size consistent with its connectiv- ity and current carrying requirements. also place the schottky di- ode as close to the phase node as possible to minimize the trace inductance, to reduce the efficiency loss due to the current ramp- up and down time. this becomes extremely important when the converter needs to handle high di/dt requirements. b. current sense. minimize the length of current sense signal trace. keep it less than 15mm. kelvin connections should be used; try to keep the traces parallel to each other and route them close to each other as much as possible. even though sc1404 implements virtual current sense scheme, the current sense signal is sampled by the sc1404 to determine the psave threshold. see the following figure for a kelvin connection of the current sense signal. c. gate drive. sc1404 has built-in gate drivers capable of sinking/sourcing 1a peaks. upper gate drive signals are noisier than the lower ones. therefore, place them away from sensitive analog circuitries. make sure the lower gate traces are as close as possible to the ic pins and both upper and lower gate traces as wide as possible. step #2: pwm controller placement (pins) and signal ground is- land. connect all analog grounds to a separate solid copper island plane, which connects to the sc1404?s gnd pin. this includes ref, comp3, comp5, sync, run/on3, on5, psv# and reset#. step #3: ground plane arrangement. there are several ways to tie the different grounds together. since this is a buck topology converter, the output ground is relatively quieter than the input ground. therefore connect analog ground to power ground at the output side. often it is useful to use a separate ground symbol for the two grounds, and tie the two grounds together at a single point through a 0 ? resistor. the power ground for the input side and the power ground for the output side is the same ground and they can be tied together using internal planes. csh csl sc1404 rcs l1
21 ? 2003 semtech corp. www.semtech.com sc1404 power management typical characteristics 3.3v efficiency 50 60 70 80 90 100 0.01 0.1 1 10 load current (a) efficiency (% ) 6v 10v 19v 5v efficiency 80 85 90 95 100 0.01 0.1 1 10 load current (a) efficiency (% ) 6v 10v 19v
22 ? 2003 semtech corp. www.semtech.com sc1404 preliminary power management evaluation board schematic 3_3v seq r22 0 ohm dh3 csh5 r23 0 ohm s1 dip_sw5_pth 1 2 3 4 5 10 9 8 7 6 on3 d6 mbrs1100t3 c13 100pf c14 100pf r12 2m 1 2 r14 2m 1 2 r15 2m 1 2 r17 2m 1 2 shdn# bst3 comp3 reset# comp5 comp3 comp5 t-on 5 bst5r ref c25 1uf/16v d4 30bq015 a c j2 gnd 1 j3 gnd 1 d2 30bq015 a c j4 gnd 1 c18 no_pop j15 shdn# 1 j5 gnd 1 j12 reset# 1 v+ r7 0.005 c9 4.7uf/35v c19 150uf/6.3v d1 bat54a bst5 l1 6.8uh 1 2 r6 0.005 vl t/ l2 tti 8215 1 5 7 4 10 6 vin jp4 1 2 lx3 dh5 j27 v+ 1 psv# j1 b_jack_pair pos 1 neg 2 dl3 u1 sc1404its csh3 1 csl3 2 comp3 3 12out 4 vdd 5 sync 6 time/on5 7 gnd 8 ref 9 psave 10 reset 11 comp5 12 csl5 13 csh5 14 seq 15 dh5 16 phase5 17 bst5 18 dl5 19 pgnd 20 vl 21 v+ 22 shdn 23 dl3 24 bst3 25 phase3 26 dh3 27 run/on3 28 lx5 r4 0 1 2 r5 0 1 2 jp1 1 2 jp2 1 2 jp3 1 2 vdd j13 t-on5 1 j11 on3 1 csh3 vin dl5 sy nc c43 no_pop c40 0.1uf vl c35 0.1uf c36 0.1uf c34 0.1uf c33 0.1uf sc1404 evb schematic c1 10uf/25v 1 2 r18 no_pop c12 0.1uf c10 0.1uf r21 no_pop r1 10 1 2 c3 0.22uf r20 no_pop r19 no_pop j16 3_3v 1 j17 csl3 1 j18 5v 1 j19 csh5 1 j20 csl5 1 j21 csh3 1 c11 4.7uf/16v c4 0.22uf d3 140t3 a c c26 0.1uf r16 1k 1 2 j6 b_jack_pair pos 1 neg 2 j7 b_jack_pair pos 1 neg 2 r13 2m 1 2 c20 no_pop c15 0.22uf c16 0.22uf d5 140t3 a c c29 no_pop c28 no_pop j22 lx3 1 j23 lx5 1 c38 1uf c39 1uf c22 4.7uf/16v c2 10uf/25v 1 2 d q1 irf7413 4 1 2 3 5 6 7 8 bst3r c42 4.7uf/25v j9 sync 1 j24 vin 1 vdd j14 vl 1 j10 psv # 1 c5 10uf/25v 1 2 c6 10uf/25v 1 2 j8 ref 1 d q2 irf7413 4 1 2 3 5 6 7 8 d q3 irf7413 4 1 2 3 5 6 7 8 3_3v 5v vl vin ref vl +12v reset# d q4 irf7413 4 1 2 3 5 6 7 8 c41 no_pop vin c37 0.01uf c17 180uf/4v j25 +12v 1 j26 gnd 1 5v c27 0.01uf
23 ? 2003 semtech corp. www.semtech.com sc1404 power management evaluation board bill of materials m e t iy t qn o i t a n g i s e dr e b m u n t r a pn o i t p i r c s e dr e r u t c a f u n a mm r o f r o t c a f 14 6 c , 5 c , 2 c , 1 c5 2 0 z 6 0 1 v 5 y 0 3 2 m r gv 5 2 , f u 0 1a t a r u m0 1 2 1 21 6 1 c , 5 1 c , 4 c , 3 c, v 0 5 , f u 2 2 . 0 v 5 y c i n o s a n a p5 0 8 39 cv 5 3 , f u 7 . 4e s a c _ b 4- 3 c , 4 3 c , 3 3 c , 6 2 c , 2 1 c , 0 1 c 0 4 c , 6 3 c , 5 r 7 x , v 0 5 , f u 1 . 0c i n o s a n a p3 0 6 0 52 2 c , 1 1 cn 0 5 2 m 5 7 4 yv 6 1 , f u 7 . 4p a c a v o n2 1 8 1 63 1 c , 4 1 ck 1 0 1 h 1 c v 1 j c ev 0 5 , f p 0 0 1c i n o s a n a p3 0 6 0 77 1 cr 1 8 1 g 0 e u - f e ev 4 , f u 0 8 1c i n o s a n a p3 4 3 7 _ e s a c _ d 89 1 cr 1 5 1 j 0 e u - f e ev 3 . 6 , f u 0 5 1c i n o s a n a p3 4 3 7 _ e s a c _ d 95 2 c5 0 1 c 1 b f 3 j c ev 6 1 , f u 1c i n o s a n a p6 0 2 1 0 17 2 c , 7 3 ck 4 0 1 c 1 b v 1 j c ev 0 5 , f u 1 0 . 0c i n o s a n a p3 0 6 0 1 18 3 c , 9 3 cf u 13 0 6 0 2 12 4 cv 5 2 , f u 7 . 4 3 111 da 4 5 t a b, a m 0 0 2 , v 0 3 e d o n a _ c l a u d x e t e z3 2 - t o s 4 12 4 d , 2 d5 1 0 q b 0 3. r . ic m s 5 12 5 d , 3 d3 t 0 4 1 s r b ma 1 , v 0 4 y k t t o h c s a l o r o t o mb m s 6 116 d3 t 0 0 1 1 s r b ma l o r o t o mb m s
24 ? 2003 semtech corp. www.semtech.com sc1404 preliminary power management m e t iy t qn o i t a n g i s e dr e b m u n t r a pn o i t p i r c s e dr e r u t c a f u n a mm r o f r o t c a f 7 14 4 p j , 3 p j , 2 p j , 1 p jg r e b n i p 2 r o t c e n n o c g r e b 8 13 7 j , 6 j , 1 jk c a j a n a n a b r i a p 9 14 27 2 j - 8 j , 5 j - 2 js t n i o p t s e t 0 211 l8 r 6 - 7 2 1 r dr o t c u d n i t m s h u 8 . 6 s c i n o r t l i o c 1 24 4 q , 3 q , 2 q , 1 q3 1 4 7 f r il e n n a h c - n v 0 3 t e f s o m l a n o i t a n r e t n i r e i f i t c e r 8 o s 2 211 ry n am h o 0 1y n a3 0 6 0 3 24 3 2 r , 2 2 r , 5 r , 4 ry n am h o 0y n a3 0 6 0 4 22 7 r , 6 r3 4 b f 5 0 0 r 2 1 5 2 l s wm h o m 5e l a d y a h s i v2 1 5 2 5 25 7 1 r , 5 1 r , 4 1 r , 3 1 r , 2 1 ry n am h o g e m 2y n a3 0 6 0 6 216 1 ry n am h o k 1y n a3 0 6 0 7 211 w sn o i t i s o p - 5 h c t i w s p i d y n a 8 2 1 2 l / t5 1 2 8 - i t tr e w o p s n a r t s e i g o l o n h c e t 9 211 us t i 4 0 4 1 c sh c e t m e s evaluation board bill of materials cont.
25 ? 2003 semtech corp. www.semtech.com sc1404 power management evaluation board gerber plots t t t t t op op op op op inner1 inner1 inner1 inner1 inner1 bottom bottom bottom bottom bottom inner2 inner2 inner2 inner2 inner2
26 ? 2003 semtech corp. www.semtech.com sc1404 preliminary power management outline drawing - ssop-28
27 ? 2003 semtech corp. www.semtech.com sc1404 power management semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805)498-2111 fax (805)498-3804 contact information outline drawing - tssop-28 land pattern - tssop-28

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